FPGA 6

• This increases the reliability when the Micro is used as a slave in a synchronised array of 1401s.

FPGA 5

• When you add a 64-channel top box you have the option of keeping the original 4 motherboard channels as 0-3 and running the top box as 4-67. However, before version 5 of the monitor and version 5 of the FPGA, channels 64-67 did not work. If your top box is set to replace the motherboard ADC channels, there will be no difference in functionality.

FPGA 4

• Corrected readback of synch state.

FPGA 3

• Fixes an occasional spurious clock 0 and 1 self test error.

FPGA 3

• Does not load the FPGA on a warm boot if already loaded.
• USB code rewritten to use a 4 endpoint interface.
• ROM,F,C,n will accept values of n from 2 to 9.
• Flash programming protects against failure caused by the MMU tables moving.
• Support for logical ADC channels added and used to add support for the ADC64 topbox.
• DAC silo support and test code added.
• USB code has watchdog to detect and react to idle.

FPGA 1

• This is the original version.