Transferências CED | História técnica do firmware Power-3

História técnica recente do firmware Power-3

Existem dois tipos de firmware no Power1401: software e hardware. O firmware do software é o código do programa que testa o Power1401 quando você o liga e que obedece às instruções transmitidas do host. O firmware de hardware inclui controles para componentes como o ADC e DACs, os relógios, a entrada e saída digital e as portas do host.

Revision 06 - Gratuito para download agora.

Se o seu número de série for inferior a P5000, consulte o histórico do Power2. Se o seu número de série for superior a P6000 consulte o Power3a.

Data	Versão	Resumo

03/21	06	Monitor 6 Changes to the EEPROM emulation did not take effect until the next power cycle. FPGA 7 Prevented a possible data corruption when both the DAC FIFO and program writes happened simultaneously to the same DAC. Corrected an error in generation of the Digital Output DTH (Data Transmitted for high byte) line.

04/14	05	Monitor 5 Improved interrupt behaviour. This significantly improves the worst case response time and slightly improves the average response time. FPGA 5 Added DAC0-ADC serial loopback controlled by FeatEn bit 7. Clock3 now has own dividers (like clock4).

11/13	04	Monitor 4 Host port idle time change; improves spike shape matching time latency in Spike2. Cache invalidation change; improves Signal dynamic clamp model updates. FPGA 4 Improvements to the DAC updating on top boxes. 8-bit DAC mode corrected.

12/12	02	Monitor 2 GAIN command adjusted to read back top box channel gains correctly. Identifies top boxes correctly when more than 1 top box is fitted.

11/12	01	Monitor 1 Improved handling of USB cable detection, single-channel ADC operation improved to allow up to 3 MHz. Boot 1 Improved 200 MHz lock detection after a reset. FPGA 2 Topbox DAC usage corrected. ADC overrun detection improved.