| layout.datehead | layout.vhead | layout.sumhead |
| 03/13 | 20 | CEDpost 0.29 Power up Self Test |
|
MonitorR 35 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 04/08 | 19 | CEDpost 0.29 Power up Self Test |
|
MonitorR 34 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 04/08 | 18 | CEDpost 0.29 Power up Self Test |
|
MonitorR 33 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 10/07 | 17 | CEDpost 0.28 Power up Self Test |
|
MonitorR 32 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 11/06 | 16 | CEDpost 0.28 Power up Self Test |
|
MonitorR 31 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 06/06 | 15 | CEDpost 0.26 Power up Self Test |
|
MonitorR 31 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 12/04 | 14 | CEDpost 0.26 Power up Self Test |
|
MonitorR 30 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 07/04 | 13 | CEDpost 0.25 Power up Self Test |
|
MonitorR 29 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 01/04 | 12 | CEDpost 0.25 Power up Self Test |
|
MonitorR 27 Monitor Pld711 20 Analogue (ANAFPGA) Pld701 17 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 04/03 | 11 | CEDpost 0.20 Power up Self Test |
|
MonitorR 24 Monitor Pld711 19 Analogue (ANAFPGA) Pld701 15 Digital (DIGFPGA) Ang285 04 Boot
|
||
| 03/03 | 10 | CEDpost 0.18 Power up Self Test |
|
MonitorR 23 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 12 Digital (DIGFPGA)
|
||
| 10/02 | 09 | CEDpost 0.18 Power up Self Test |
|
MonitorR 22 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 12 Digital (DIGFPGA)
|
||
| 07/02 | 08 | CEDpost 0.17 Power up Self Test |
|
MonitorR 22 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 12 Digital (DIGFPGA)
|
||
| 03/02 | 07 | CEDpost 0.16 Power up Self Test |
|
MonitorR 22 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 10 Digital (DIGFPGA)
|
||
| 02/02 | 06 | CEDpost 0.15 Power up Self Test |
|
MonitorR 21 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 10 Digital (DIGFPGA)
|
||
| 07/01 | 05 | CEDpost 0.14 Power up Self Test |
|
MonitorR 20 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 10 Digital (DIGFPGA)
|
||
| 05/01 | 04 | CEDpost 0.14 Power up Self Test |
|
MonitorR 19 Monitor Pld711 16 Analogue (ANAFPGA) Pld701 10 Digital (DIGFPGA)
|
||
| 09/00 | 03 | CEDpost 0.10 Power up Self Test |
|
MonitorR 15 Monitor Pld711 12 Analogue (ANAFPGA) Pld701 10 Digital (DIGFPGA)
|
||
| 08/00 | 02 | CEDpost 0.09 Power up Self Test |
|
MonitorR 15 Monitor Pld711 12 Analogue (ANAFPGA) Pld701 09 Digital (DIGFPGA)
|
||
| 06/00 | 01 | CEDpost 0.06 Power up Self Test |
|
MonitorR 13 Monitor Pld711 10 Analogue (ANAFPGA) Pld701 09 Digital (DIGFPGA)
|
||
manualsmenu.engonly
© home.copyright CED 2025
layout.reginengland: 00972132
layout.regoffice:
- Cambridge Electronic Design Limited,
- Technical Centre,
- 139 Cambridge Road,
- Milton,
- Cambridge CB24 6AZ
- ENGLAND.
VAT: GB 214 2617 96
layout.prodregno: WEE/BD0050TZ
layout.forourus.
CAGE/NCAGE: KB797
NAICS: 423490
Hardware: 84716070
Software: 85235190
support.email
support.post
- Cambridge Electronic Design Limited,
- Technical Centre,
- 139 Cambridge Road,
- Milton,
- Cambridge CB24 6AZ
- ENGLAND.
support.tel
(Int.+44) (0)1223 420186
support.tollfree
1 800 345 7794