Transferências CED | História técnica do firmware Power-mkII

História técnica recente do firmware Power-mkII

Existem dois tipos de firmware no Power1401: software e hardware. O firmware do software é o código do programa que testa o Power1401 quando você o liga e que obedece às instruções transmitidas do host. O firmware de hardware inclui controles para componentes como o ADC e DACs, os relógios, a entrada e saída digital e as portas do host.

Revision 09 - Gratuito para download agora.

Se o seu número de série for inferior a P4000, consulte o histórico do Power1401 mk1. Se o seu número de série for soperior a P5000 consulte o Power3.

Data	Versão	Resumo
03/10	09	Monitor 8 Experimental cache locking added plus floating-point support. Loaded commands are aligned to a cache line (32-byte) boundary. FPGA 9 Fixed problem with DAC FIFO scheme - DAC outputs could freeze up.

11/09	08	Monitor 7 FPGA data is only loaded if not already loaded. The USB code has been rewritten to use 4 endpoint interface with idle watchdog code. DAC silo support and test code added.

10/09	07	Monitor 6
		FPGA 8 Added support for DAC Silo scheme (not yet supported by software). Changes to overcome Issue C board problems.

10/08	06	Monitor 6 Code emulating EEPROMs in flash memory improved to avoid problems with EEPROM writes. Cache flush function adjusted to avoid possible MEMDAC problems if interrupts running. I2C bus access functions added to symbol table for access by commands. 1-wire interface functions written and added to symbol table. Extended self-test code for clocked ADC conversions. FPGA 6 Behaviour of clock 4 flag corrected. 100 ns pulses for digital I/O generated correctly.

06/08	05	Monitor 5
		FPGA 5 Clock timing tightened to avoid spurious overrun errors. OVRSRC register added.

04/08	04	Monitor 5 Gives better information if an interrupt overrun occurs.

04/08	03	Monitor 4 Provides scatter/gather data transfer mechanisms for transfers to host PC. More resistant to external event pulses during self-test.

11/07	02	Monitor 3
		FPGA 4 Changes made for 8-bit DAC writes.

10/07	01	Monitor 3 SetADClist extended to support sub-bursts. Slightly relaxed analogue self-test limits. Error LED operations corrected. Clear flash memory slot n code added. FPGA 3 Improved timing for HSS interface so as to work on Test-Rack. Fixed addressing problem for systems with more than 1 top-box.