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Recent technical history of Power1401 mkII firmware

There are two types of firmware in the Power1401: software and hardware. The software firmware is the program code that tests the Power1401 when you switch it on and that then obeys instructions transmitted from the host. The hardware firmware includes controls for components such as the ADC and DACs, the clocks, the digital input and output, and the host ports.

Revision 09 - Freely downloadable now.

If your serial number is below P4000, see the history of the Power1401 mk1. If above P5000 see the Power3.


Date Version Summary
03/10 09 Monitor 8
  • Experimental cache locking added plus floating-point support. Loaded commands are aligned to a cache line (32-byte) boundary.
FPGA 9
  • Fixed problem with DAC FIFO scheme - DAC outputs could freeze up.
11/09 08 Monitor 7
  • FPGA data is only loaded if not already loaded.
  • The USB code has been rewritten to use 4 endpoint interface with idle watchdog code.
  • DAC silo support and test code added.
10/09 07 Monitor 6
FPGA 8
  • Added support for DAC Silo scheme (not yet supported by software).
  • Changes to overcome Issue C board problems.
10/08 06 Monitor 6
  • Code emulating EEPROMs in flash memory improved to avoid problems with EEPROM writes.
  • Cache flush function adjusted to avoid possible MEMDAC problems if interrupts running.
  • I2C bus access functions added to symbol table for access by commands.
  • 1-wire interface functions written and added to symbol table.
  • Extended self-test code for clocked ADC conversions.
FPGA 6
  • Behaviour of clock 4 flag corrected.
  • 100 ns pulses for digital I/O generated correctly.
06/08 05 Monitor 5
FPGA 5
  • Clock timing tightened to avoid spurious overrun errors.
  • OVRSRC register added.
04/08 04 Monitor 5
  • Gives better information if an interrupt overrun occurs.
04/08 03 Monitor 4
  • Provides scatter/gather data transfer mechanisms for transfers to host PC.
  • More resistant to external event pulses during self-test.
11/07 02 Monitor 3
FPGA 4
  • Changes made for 8-bit DAC writes.
10/07 01 Monitor 3
  • SetADClist extended to support sub-bursts.
  • Slightly relaxed analogue self-test limits.
  • Error LED operations corrected.
  • Clear flash memory slot n code added.
FPGA 3
  • Improved timing for HSS interface so as to work on Test-Rack.
  • Fixed addressing problem for systems with more than 1 top-box.
Cambridge Electronic Design Limited

Registered in England: 00972132

Registered office:

  • Cambridge Electronic Design Limited,
  • Technical Centre,
  • 139 Cambridge Road,
  • Milton,
  • Cambridge CB24 6AZ
  • ENGLAND.

VAT: GB 214 2617 96

Producer registration number: WEE/BD0050TZ

Terms and Conditions of Sale

For our US customers, we can provide tax form W-8BEN, that identifies us as a UK company.

DUNS: 219151016
CAGE/NCAGE: KB797
NAICS: 423490
Commodity codes
Hardware: 84716070
Software: 85234945
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By email:

info@ced.co.uk

By post:
  • Cambridge Electronic Design Limited,
  • Technical Centre,
  • 139 Cambridge Road,
  • Milton,
  • Cambridge CB24 6AZ
  • ENGLAND.
By telephone:

(Int.+44) (0)1223 420186

From North America (Toll Free):

1 800 345 7794

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