CED Downloads | Power1401-3 firmware technical history

Recent technical history of Power1401-3 firmware

There are two types of firmware in the Power1401: software and hardware. The software firmware is the program code that tests the Power1401 when you switch it on and that then obeys instructions transmitted from the host. The hardware firmware includes controls for components such as the ADC and DACs, the clocks, the digital input and output, and the host ports.

Revision 06 - Freely downloadable now.

If your serial number is below P5000, see the history of the Power2. If above P6000 see the Power3A.

Date	Version	Summary

03/21	06	Monitor 6 Changes to the EEPROM emulation did not take effect until the next power cycle. FPGA 7 Prevented a possible data corruption when both the DAC FIFO and program writes happened simultaneously to the same DAC. Corrected an error in generation of the Digital Output DTH (Data Transmitted for high byte) line.

04/14	05	Monitor 5 Improved interrupt behaviour. This significantly improves the worst case response time and slightly improves the average response time. FPGA 5 Added DAC0-ADC serial loopback controlled by FeatEn bit 7. Clock3 now has own dividers (like clock4).

11/13	04	Monitor 4 Host port idle time change; improves spike shape matching time latency in Spike2. Cache invalidation change; improves Signal dynamic clamp model updates. FPGA 4 Improvements to the DAC updating on top boxes. 8-bit DAC mode corrected.

12/12	02	Monitor 2 GAIN command adjusted to read back top box channel gains correctly. Identifies top boxes correctly when more than 1 top box is fitted.

11/12	01	Monitor 1 Improved handling of USB cable detection, single-channel ADC operation improved to allow up to 3 MHz. Boot 1 Improved 200 MHz lock detection after a reset. FPGA 2 Topbox DAC usage corrected. ADC overrun detection improved.