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The Power1401 has five clocks, used for timing and counting external pulses (clocks 0 and 1), generating general purpose timing pulses (clock 2), controlling waveform output (clocks 3 and 4) and controlling the waveform input sampling rate (clock 4).

Power1401 front clocks

These clocks are managed automatically by the application software. You may need to drive a clock from an experiment, e.g. to trigger sweeps of waveform sampling. The front-panel Trigger input will be routed by software to the correct clock, to set it running on your signal.

You may require the application to generate pulses to drive an experiment. The output of Clock 2 is available from the front-panel Clock BNC connector. The application manual describes this where it is relevant.

Where external signal pulses are to be timed or counted, the application program may use the front-panel Event 0 and Event 1 inputs. Pulses must be 1microSec or wider. If there are more than two such signals, the rear-panel Digital Inputs may be used.

All clock frequencies are normally derived from an internal crystal oscillator. Users may sometimes need to take a timing source from outside the Power1401 instead. All the clocks can be driven from an external frequency source via the Clock F input, pin 7 on the rear-panel Events socket. When you need to synchronise two 1401 machines, connect the 4MHz Clock output from one to the F input of the other.


The trigger and event-input LEDs flash on detection of an active-edge transition. These LEDs can be either on or off in the quiescent state, as set by software command, to indicate that the input is armed and expects to be used. The clock output LED simply indicates that Clock 2 is running, turning on whenever Clock 2 is enabled.

Technical details

Event 0 and Event 1 have in-line over-voltage protection and can accept signals in a ±40V range (absolute maximum). These inputs are held internally to +5V by 100 kOhm resistors and have input hysteresis: the low-going threshold voltage is set at 0.95V and the high-going threshold at 1.2V. To pull these inputs low, the driving device must be able to sink 50microA. Pulses driving these front panel inputs must be 1microSec or longer. Clock is an output, driven by a 74ACT374 bus driver element which can source or sink 24mA.

Event inputs

More clock-related inputs, the Clock E series, are provided on the rear-panel Events D-socket. These inputs allow close control of the clocks for people writing their own software. Full details are given in the 1401 family programming manual. The front panel BNCs Event 0 and Event 1 are often routed by software to the Clock E0 and E1 inputs.

Power1401 rear Events
Technical details

Clock E and Clock F inputs respond to TTL or switch closure signals, and are held internally to +5V by 10 kOhm resistors. To pull these inputs low, the driving device must be able to sink at least 500microA; input pulses must fall below 0.8V to guarantee recognition. Clock E pulses should not be narrower than 100ns. Clock F frequency must not exceed 10MHz; pulses should be wider than 50ns. The working range of these inputs is 0 to +5V. They are protected by a 100 Ohm resistor in series with diode clamps to +5V and ground; the safe input range is ±10V. All chips associated with the Events I/O are in sockets for easy replacement.

The 4MHz Clock output signal is buffered by a NC7SZ04 Schmidt inverter element which can drive 10 LS TTL loads. 4 MHz Clock can be isolated from the rear-panel socket by a cuttable link, to help reduce EMI.

The sense of the Clock E and ADC external convert inputs may be inverted by a switch option, but the inputs would all then be held active high if no input is connected.

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